Basic VLSI Design by Douglas A. Pucknell PDF

By Douglas A. Pucknell

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After exposure to the E-beam, the plates are introduced into a developer to bring out the patterns left by the E-beam in the resist coating. 5. The cycle is followed by a bake cycle and a plasma de-summing, which removes the resist residue. 6. The chrome is then etched and the plate is stripped of the remaining E-beam resist. The advantages of E-beam masks are: • tighter layer to layer registration; • smaller feature sizes. There are two approaches to the design of E-beam machines: • raster scanning; • vector scanning.

D) If VGG is higher than VDD then an extra supply rail is required. 4. 14). (a) No current flow either for logical 0 or for logical 1 inputs. (b) Full logical 1 and 0 levels are presented at the output. (c) For devices of similar dimensions the p-channel is slower than the n-channel device. -· ,. \,. 14 4 "'n Complementary transistor pull-up (CMOS). 14. 5) that the current/voltage relationships for the MOS transistor may be written in the resistive region, or in saturation. ) I in saturation, and where 1t may be applied to both nMOS and pMOS transistors as follows: where Wn and Lm WP and LP are the n- and p-transistor dimensions respectively.

2 MOS transistor characteristics . vP Basic Electrical Properties of MOS and BiCMOS Circuits C0 = ms = JN = ••• capacitance per unit gate area work function difference between gate and Si Fermi level potential between inverted surface and bulk Si. Now, for polysilicon gate and silicon substrate, the value of ms is negative but negligible, and the magnitude and sign of V1 are thus determined by the balance between the remaining negative term -Qss and the other two terms, both of which are positive.

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Basic VLSI Design by Douglas A. Pucknell


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